1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically to a technique of reducing the area of a peripheral circuit region with respect to a pixel region that has one or more pixels. The present invention also relates to a technique of improving an aperture ratio of the pixel region by giving the peripheral circuit region (“border frame”) a smaller width through a multilayer wiring.
2. Description of the Related Art
FIG. 6 is a plan view schematically showing a chip in a conventional liquid crystal display device.
This chip in the liquid crystal display device has a pixel region 101, which has a square shape in plan view. The pixel region 101 is composed of one or more pixels. Placed in the periphery (above, to the left, and to the right) of the pixel region 101 are peripheral circuits 102a to 102c. The chip is arranged on a substrate (or this chip and similar chips are arranged on the same substrate). The peripheral circuits 102a to 102c each have a thin rectangular shape in plan view, and the shorter sides of each rectangular are 2 to 3 mm in length. The reason each of the peripheral circuits needs a width of 2 to 3 mm is because power supply lines, clock lines, and other wirings formed in the peripheral circuit are on the order of tens to hundreds of μm in width, thus taking up a large area.
The peripheral circuits 102a to 102c have TFTs (thin film transistors). Those TFTs have gate electrodes formed from a refractory metal such as polysilicon or W. The gate electrodes are for applying a gate voltage to specific TFT active layers, and the gate electrodes of the plural TFTs are electrically connected with one another. The gate electrodes are electrically connected to intersecting wirings. The wirings electrically connect the plural TFTs with one another, and are placed in a layer above the gate electrodes. The wirings also connect the TFTs to pixel electrodes. The wirings have a laminated structure composed of, for example, an Al film and a barrier metal film. The barrier metal film is a single layer or a multilayer structure of Ti, TiN, Ta, TaN, W, or the like.
Formed in a layer above the wiring layer is a black mask, which is an Al film or the like. The black mask has a light-shielding function and an electric potential blocking ability. A pixel electrode is formed from ITO in a layer above the black mask.
[Reference 1: JP 09-43630 A ]
As mentioned above, the peripheral circuit region (the peripheral circuits constituting a “border frame” around the pixel region) has a width of 2 to 3 mm. Because, the peripheral circuit region is desired to have a narrower width because reduction in width of the peripheral circuit region (border frame) leads to an improvement in aperture ratio of the pixel region. To elaborate, reduction in width of the peripheral circuit region gives the pixel region a larger area when the chip size is equal and accordingly the area of each pixel is increased, thus increasing the area of the aperture in each pixel and improving the brightness. On the other hand, when the pixel region has the same area, reduction in width of the peripheral circuit region makes it possible to reduce the chip size and the chip becomes more suitable for mass production.
In the conventional liquid crystal display device described above, the wiring layer is a single layer and raising the degree of integration in the wiring layer is difficult due to limitations of a photolithography system or the like. When wirings are formed in the same layer, the wirings take up a large area and the proportion of the area of the driver circuit and other peripheral circuits to the entire chip area is accordingly large, presenting an obstacle to reduction in width of the peripheral circuit region.
When the peripheral circuit region has a large width, the wirings electrically connecting plural pixels with one another also tend to have an extended length since the wirings run across the pixel region. This could result in higher-than-ideal resistance for the wirings and a shortage of current to be supplied to the TFTs.
In addition, the gate electrodes formed in a layer below the wirings tend to be made thicker in order to lower the resistance of the gate electrodes. Thicker gate electrodes increase the level difference in the base of the wiring layer to reduce the patterning margin in forming the wirings. This could result in level discontinuity in the wirings patterned.